drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35
- Published
- Last modified
- Where the record stands: published, rejected by its publisher, or superseded by another id.What do these mean? →
- published
- Whether CISA lists it in its Known Exploited Vulnerabilities catalog: proof that attackers are using it.What do these mean? →
- Not listed in CISA KEV
- Fix
- Fixed in 6.12.114, 6.18.57, 6.19.6
- Whether working attack code is public (Exploit-DB, Metasploit, Nuclei or GitHub). Public code makes attacks easier.What do these mean? →
- None on Exploit-DB, Metasploit or GitHub
Summary
In the Linux kernel, the following vulnerability has been resolved: drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35 [Why] A backport of the change made for DCN401 that addresses an issue where we turn off the PHY PLL when disabling TMDS output, which causes the OTG to remain stuck. The OTG being stuck can lead to a hang in the DCHVM's ability to ACK invalidations when it thinks the HUBP is still on but it's not receiving global sync. The transition to PLL_ON needs to be atomic as there's no guarantee that the thread isn't pre-empted or is able to complete before the IOMMU watchdog times out. [How] Backport the implementation from dcn401 back to dcn35. There's a functional difference in when the eDP output is disabled in dcn401 code so we don't want to utilize it directly.
Timeline
- CVE published
- Record last updated
Affected versions
- Linux Linux
From ec129fa356bea5411cb16833cc5dab32689ea389 · fixed in be43c36ac13d3a158791566c9fe60511022b7a15; From ec129fa356bea5411cb16833cc5dab32689ea389 · fixed in 02b033e18e08a1d0b53cf540196688c82af60a2f; From ec129fa356bea5411cb16833cc5dab32689ea389 · fixed in d1f7ceb00e8956ff6d183b7b45ef4e73c96f4c51; From ec129fa356bea5411cb16833cc5dab32689ea389 · fixed in 75372d75a4e23783583998ed99d5009d555850da
- Linux Linux
6.7
- KernelLinux
From 6.7.0 · fixed in 6.12.114; From 6.13.0 · fixed in 6.18.57; From 6.19.0 · fixed in 6.19.6